Manpages of PrimeTime Variables pdf file for download.
This pdf document is download from www.cadfamily.com/download/eda/icc/pt3.pdf
Local download link: PrimeTime-Variables.pdf
PrimeTime Variables List:
Manpages of PrimeTime Variables pdf file for download.
This pdf document is download from www.cadfamily.com/download/eda/icc/pt3.pdf
Local download link: PrimeTime-Variables.pdf
PrimeTime Variables List:
arch
auto_link_disable
auto_wire_load_selection
bus_naming_style
case_analysis_log_file
case_analysis_propagate_through_icg
case_analysis_sequential_propagation
ccs_noise_small_bump_threshold_ratio
collection_deletion_effort
collection_result_display_limit
create_clock_no_input_delay
dbr_ignore_external_links
default_oc_per_lib
disable_case_analysis
disable_case_analysis_ti_hi_lo
eco_instance_name_prefix
eco_net_name_prefix
eco_write_changes_prepend_libfile_to_libcell
enable_license_auto_reduction
enable_page_mode
extract_model_capacitance_limit
extract_model_clock_transition_limit
extract_model_data_transition_limit
extract_model_enable_report_delay_calculation
extract_model_gating_as_nochange
extract_model_include_ideal_clock_network_latency
extract_model_keep_inferred_nochange_arcs
extract_model_lib_format_with_check_pins
extract_model_merge_clock_gating
extract_model_noise_iv_index_lower_factor
extract_model_noise_iv_index_upper_factor
extract_model_noise_width_points
extract_model_num_capacitance_points
extract_model_num_clock_transition_points
extract_model_num_data_transition_points
extract_model_num_noise_iv_points
extract_model_num_noise_width_points
extract_model_single_pin_cap
extract_model_single_pin_cap_max
fextract_model_split_partial_clock_gating_arcs
extract_model_status_level
extract_model_suppress_three_state
extract_model_use_conservative_current_slew
extract_model_with_3d_arcs
extract_model_with_clock_latency_arcs
extract_model_write_case_values_to_constraint_file
hier_scope_check_defaults
hierarchy_separator
ilm_ignore_percentage
ilm_write_verilog_logic_constant_net_names
in_gui_session
lib_thresholds_per_lib
link_create_black_boxes
link_force_case
link_library
link_path
link_path_per_instance
multi_scenario_merged_error_limit
multi_scenario_merged_error_log
multi_scenario_message_verbosity_level
multi_scenario_working_directory
mw_design_library
mw_logic0_net
mw_logic1_net
parasitics_cap_warning_threshold
parasitics_rejection_net_size
parasitics_res_warning_threshold
parasitics_warning_net_size
pba_disable_path_recalculation_limit
pba_enable_ccs_waveform_propagation
pba_enable_path_based_physical_exclusivity
pba_enable_xtalk_delay_ocv_pessimism_reduction
pba_exhaustive_endpoint_path_limit
pba_recalculate_full_path
power_average_waveform_limit
power_calc_use_ceff_for_internal_power
power_check_defaults
power_clock_network_include_clock_gating_network
power_clock_network_include_register_clock_pin_power
power_default_static_probability
power_default_toggle_rate
power_default_toggle_rate_reference_clock
power_domains_compatibility
power_enable_analysis
power_enable_analysis
power_estimate_power_for_unmatched_event
power_force_saif_flow
power_include_initial_x_transitions
power_leakage_variation_interpolation_methods
power_limit_extrapolation_range
power_match_state_for_logic_x
power_model_preference
power_rail_output_file
power_read_activity_ignore_case
power_report_leakage_breakdowns
power_reset_negative_extrapolation_value
power_reset_negative_internal_power
power_scale_dynamic_power_at_power_off
power_table_include_switching_power
power_x_transition_derate_factor
pt_ilm_dir
pt_shell_mode
pt_tmp_dir
ptxr_root
ptxr_setup_file
rc_adjust_rd_when_less_than_rnet
rc_always_use_max_pin_cap
rc_cache_min_max_rise_fall_ceff
rc_ceff_delay_min_diff_ps
rc_ceff_use_delay_reference_at_cpin
rc_create_and_cache_pi_models
rc_degrade_min_slew_when_rd_less_than_rnet
rc_driver_count_threshold_for_fast_multidrive_analysis
rc_driver_model_max_error_pct
rc_driver_model_mode.
rc_filter_rd_less_than_rnet
rc_hide_ceff_warnings_for_enable_arcs
rc_input_threshold_pct_fall
rc_input_threshold_pct_rise
rc_output_threshold_pct_fall
rc_output_threshold_pct_rise
rc_rd_less_than_rnet_threshold
rc_receiver_model_mode
rc_slew_derate_from_library
rc_slew_lower_threshold_pct_fall
rc_slew_lower_threshold_pct_rise
rc_slew_upper_threshold_pct_fall
rc_slew_upper_threshold_pct_rise
read_parasitics_load_locations
report_default_significant_digits
sdc_save_source_file_information
sdc_version
sdc_write_unambiguous_names
sdf_align_multi_drive_cell_arcs
sdf_align_multi_drive_cell_arcs_threshold
sdf_annotate_cond_specific_delays
sdf_enable_cond_start_end
sdf_enable_port_construct
sdf_enable_port_construct_threshold
search_path
sh_eco_enabled
sh_enable_line_editing
sh_high_capacity_effort
sh_high_capacity_enabled
sh_launch_dir
sh_limited_messages
sh_line_editing_mode
sh_message_limit
sh_output_log_file
si_analysis_logical_correlation_mode
si_ccs_aggressor_alignment_mode
si_ccs_use_gate_level_simulation
si_enable_analysis
si_filter_accum_aggr_noise_peak_ratio
si_filter_per_aggr_noise_peak_ratio
si_filter_per_aggr_to_average_aggr_xcap_ratio
si_filter_per_aggr_xcap
si_filter_per_aggr_xcap_to_gcap_ratio
si_filter_total_aggr_xcap
si_filter_total_aggr_xcap_to_gcap_ratio
si_ilm_keep_si_user_excluded_aggressors
si_noise_composite_aggr_mode
si_noise_effort_threshold_beyond_rails
si_noise_effort_threshold_within_rails
si_noise_endpoint_height_threshold_ratio
si_noise_limit_propagation_ratio
si_noise_nmos_threshold_ratio
si_noise_pmos_threshold_ratio
si_noise_slack_skip_disabled_arcs
si_noise_total_effort_threshold_beyond_rails
si_noise_total_effort_threshold_within_rails
si_noise_update_status_level
si_use_driving_cell_derate_for_delta_delay
si_xtalk_analysis_effort_level
si_xtalk_calculate_macro_model_delta_transition
si_xtalk_composite_aggr_mode
si_xtalk_composite_aggr_noise_peak_ratio
si_xtalk_composite_aggr_quantile_high_pct
si_xtalk_delay_analysis_mode
si_xtalk_double_switching_mode
si_xtalk_exit_on_coupled_reevaluated_nets_pct
si_xtalk_exit_on_max_delta_delay
si_xtalk_exit_on_max_iteration_count
si_xtalk_exit_on_max_iteration_count_incr
si_xtalk_exit_on_min_delta_delay
si_xtalk_exit_on_number_of_reevaluated_nets
si_xtalk_exit_on_reevaluated_nets_pct
si_xtalk_reselect_clock_network
si_xtalk_reselect_critical_path
si_xtalk_reselect_delta_and_slack
si_xtalk_reselect_delta_delay
si_xtalk_reselect_delta_delay_ratio
si_xtalk_reselect_max_mode_slack
si_xtalk_reselect_min_mode_slack
si_xtalk_reselect_time_borrowing_path
svr_enable_vpp
svr_keep_unconnected_nets
timing_all_clocks_propagated
timing_allow_short_path_borrowing
timing_aocvm_analysis_mode
timing_aocvm_enable_analysis
timing_bidirectional_pin_max_transition_checks
timing_check_defaults
timing_clock_gating_propagate_enable
timing_clock_reconvergence_pessimism
timing_clock_source_driver_pin_use_driver_arc_compatibility
timing_crpr_enable_adaptive_engine
timing_crpr_remove_clock_to_data_crp
timing_crpr_remove_muxed_clock_crp
timing_crpr_threshold_ps
timing_disable_bus_contention_check
timing_disable_clock_gating_checks
timing_disable_cond_default_arcs
timing_disable_floating_bus_check
timing_disable_internal_inout_cell_paths
timing_disable_internal_inout_net_arcs
timing_disable_recovery_removal_checks
timing_dynamic_loop_breaking
timing_early_launch_at_borrowing_latches
timing_edge_specific_source_latency
timing_enable_clock_propagation_through_preset_clear
timing_enable_clock_propagation_through_three_state_enable_pins
timing_enable_constraint_delay_calculation_compatibility
timing_enable_invalid_slew_propagation_compatibility
timing_enable_max_capacitance_set_case_analysis
timing_enable_multiple_clocks_per_reg
timing_enable_preset_clear_arcs
timing_enable_pulse_clock_constraints
timing_gclock_source_network_num_master_registers
timing_ideal_clock_zero_default_transition
timing_include_available_borrow_in_slack
timing_input_port_clock_shift_one_cycle
timing_input_port_default_clock
timing_keep_loop_breaking_disabled_arcs
timing_non_unate_clock_compatibility
timing_prelayout_scaling
timing_propagate_interclock_uncertainty
timing_propagate_through_non_latch_d_pin_arcs
timing_propagate_through_unclocked_registers
timing_reduce_multi_drive_net_arcs
timing_reduce_multi_drive_net_arcs_threshold
timing_remove_clock_reconvergence_pessimism
timing_report_always_use_valid_start_end_points
timing_report_maxpaths_nworst_reached
timing_report_recalculation_status
timing_report_status_level
timing_report_unconstrained_paths Specifies if
timing_report_use_worst_parallel_cell_arc
timing_save_pin_arrival_and_required
timing_save_pin_arrival_and_slack
timing_si_exclude_delta_slew_for_transition_constraint
timing_slew_propagation_mode
timing_slew_threshold_scaling_for_max_transition_compatibility
timing_update_default_mode
timing_update_effort
timing_update_status_level
timing_use_zero_slew_for_annotated_arcs
true_delay_prove_false_backtrack_limit
true_delay_prove_true_backtrack_limit
variation_analysis_mode
variation_derived_scalar_attribute_mode
variation_enable_analysis
variation_report_timing_increment_format
write_script_include_library_constraints
write_script_output_lumped_net_annotation