Clock Latency

Clock Latency contain following two parts:

• Network Latency: net delay from clock port to flip-flop clock pin in the design.
• Source Latency:   delay from clock source to design clock port.

Clock Latency contain following two parts:

• Network Latency: net delay from clock port to flip-flop clock pin in the design.
• Source Latency:   delay from clock source to design clock port.

See pic for detail information for clock latency:

Ideal Clock has zero latency

• http://vlsi-concept.blogspot.com/2008/12/ideal-clock-feature.html