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- chip specification;
- front end modeling, use C, C++ or System C/system verilog to do the modeling and simulation;
- design implementation in front end, verilgo or VHDL ;
- simulation;
- FPGA verification(optional);
- Synthesis, Design compiler , RTL to gate level netlist;
- Physical implementation.
- chip specification;
- front end modeling, use C, C++ or System C/system verilog to do the modeling and simulation;
- design implementation in front end, verilgo or VHDL ;
- simulation;
- FPGA verification(optional);
- Synthesis, Design compiler , RTL to gate level netlist;
- Physical implementation.
- Post simulation ( simulation with back-annotate SDF)
- signoff ( StarRCXT, PrimeTime, Hercules).
- set data to foundry ( GDSII file ), OPC.
- manufacturing.
- Test and packaging.