ASIC Design Implementation Flow In Brief

  1. design setup;
  2. floorplan;
  3. placement;
  4. Clock Tree synthesis (CTS);
  5. routing;
  6. chip finishing( insert diode, insert filler, insert metal filler, add redundant via …);
  7. signoff flow ( StarRCXT, PT, DRC, LVS).

  1. design setup;
  2. floorplan;
  3. placement;
  4. Clock Tree synthesis (CTS);
  5. routing;
  6. chip finishing( insert diode, insert filler, insert metal filler, add redundant via …);
  7. signoff flow ( StarRCXT, PT, DRC, LVS).

Leave a Reply

Your email address will not be published. Required fields are marked *