Clock Latency contain following two parts:
- Network Latency: net delay from clock port to flip-flop clock pin in the design.
- Source Latency: delay from clock source to design clock port.
Definition of Timing Path
优盘（U盘）检测软件
http://www.mydigit.cn/mydisktest.htm
优盘检测软件，
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utf8编码的中文分词词库下载
Ideal Clock Feature
Feature of ideal clock:
- Infinite drive capability
- Zero rise/fall transition times
- Zero skew
- Zero insertion delay or latency
For ideal network feature: http://vlsi-concept.blogspot.com/2008/12/ideal-network-feature.html
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filter_collection 可以使用的操作符
概览
==, !=, >, < , >=, < =, =~, !~ 解释
== 等于
!= 不等于
> 大于
< 小于
>= 大于等于
< = 小于等于
=~ 匹配
!~ 不匹配
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difference between dc_shell and dc_shell-t
The "-t" extension invokes DC shell in Tcl-mode, which is the
recommended mode, and by default, also XG mode, which is also
recommended. Design Vision is ONLY available in TCL mode, hence no
"-t" extension is needed, and it also comes up in XG mode by default.
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WLM- Wire load Model
在没有物理信息的时候，使用Wire load Model（WLM）模型可以算到net的电容，电阻等数据。所以在DC中会使用WLM模型。
Design Compiler Topographical Technology
Topographical technology enables you to accurately predict post-layout timing, area, and power during RTL synthesis without the need for wireload model-based timing approximations. It uses Synopsys’ placement and optimization technologies to drive accurate timing prediction within synthesis, ensuring better correlation to the final physical design.
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Synopsys Implementation Tool Guide
Synopsys Implementation Tool Guide
Design Compiler – Logic synthesis
Design Compiler Topographical — DCT(new feature)
Physical Compiler – Physical synthesis
JupiterXT – Floorplanning
Astro – Place and Route for designs down to 65nm design rules
IC Compiler – Next generation Place & Route
Continue reading “Synopsys Implementation Tool Guide”