The MinWidth of POLY layer represent the process technology.
See following example:
Continue reading “How to read ITF file to find the process technology”
What does ’45-nm’ mean
So today, "65 nm" or "45 nm" doesn’t exactly refer to the line width, and certainly doesn’t indicate how closely you can pack transistors together, although it does provide some indication of these things. Still, it is probably most accurate to say that the number is simply the name of the process, rather than the measure of any particular feature.
Clear Type 调整器
现在我们一般用的都是液晶显示器，但有时候我们会发现液晶显示器显示的文字会发虚，很模糊，看不清楚。
这其实不是显示器的原因，而是我们没有设置好。
此时我们就需要使用Clear Type调整器来进行调整。
下面这个页面给我们说明了调整器的下载和使用方法。
Cell Degradation Design Rule
The standard design rules (max_transition, max_fanout, and max_capacitance) cannot account for all reliability issues in deep submicron technologies.A new design rule was introduced to model this behavior more accurately.
显卡上的S/PDIF接口
今天帮同事买了块华硕EN9600GT冰刃版的显卡，看到有个S/PDIF接口，感到很郁闷，为什么显卡会有音频接口呢。
后来查了一下，这是块支持HDTV的显卡，附有1个 DVI转HDMI转接头 和1 个 HDTV输出信号线，需要将音频输出到电视机的话就要链接S/PDIF。
Continue reading “显卡上的S/PDIF接口”
Timing Arc
Timing Arc Definition:
Timing arcs, along with netlist interconnect information, are the paths followed by the path tracer during path analysis.
Each timing arc has a startpoint and an endpoint.
Continue reading “Timing Arc”
cell degradation
A cell degradation design rule specifies the maximum capacitive load a cell can drive without causing cell performance degradation during the fall transition.
But I don’t know the difference between cell degradation and max capacitance constraint rule:(
Virtual Clock
Virtual clock feature:
- A clock that is not connected to any port or pin within the current design
- Serves as a reference for input or output delays
difference between real clock and ideal clock
Ideal Network Feature
Ideal Network Feature:
- No DRC (capacitance, fanout, and transition) check for ideal net.
- Zero pin capacitance and net capacitance for timing calculation.