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- 优惠券有效期：2008年12月31日–2009年2月28日
- 优惠券金额： 5元
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- 每张订单限用一张动感时尚优惠券
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Month: February 2009
2008年12月29日上海市最新税费征收方式
注意：
1、根据上海市政府2008年12月28日出台的八条政策，对比原来的征收方式，特制定上述税费计算表，各业务单位可与各区交易员确认。
2、该征收方式自2009年1月1日起，各交易中心正式执行；
3、和原征收方式比较在普通住宅营业税、非普通住宅营业税、个人所得税、和90平米的改善型住宅的契税做出了调整，具体内容已经用红色字体标注出来，请大家仔细阅读。
4、上海市各区公积金贷款自2009年1月1日起，需要凭抵押权证才能放款，原来见收件收据放款取消，请业务单位注意；
5、上述政策的执行时间为2009年1月1日至2009年12月31日。
短url的开源源代码
短url的好处就不用说了，
容易记，
在邮件中不会折行，
……
在邮件中不会折行，
……
短url的老大是http://tinyurl.com/，但是如果你想自己做一个缩短网址的网站，其实也很简单。
去http://lilurl.sourceforge.net/下载一个缩短网址的源代码，自己安装一下。
我自己也写了做了一个缩短网址，实现短url的网站，
网站连接如下： http://u9d.cn/ 意思为 “U就短”
Continue reading “短url的开源源代码”
Physical Design Rule
What’s Physical Design Rule
1. Interface between the circuit designer and process engineer
2. Guidelines for constructing process masks
3. Unit dimension: minimum line width
2. Guidelines for constructing process masks
3. Unit dimension: minimum line width
scalable design rules: lambda parameter
absolute dimensions: micron rules
absolute dimensions: micron rules
4. Rules constructed to ensure that design works even when small fab errors (within some tolerance) occur
5. A complete set includes
5. A complete set includes
set of layers
intra-layer: relations between objects in the same layer
inter-layer: relations between objects on different layers
intra-layer: relations between objects in the same layer
inter-layer: relations between objects on different layers
ASIC Design Implementation Flow In Brief
- design setup;
- floorplan;
- placement;
- Clock Tree synthesis (CTS);
- routing;
- chip finishing( insert diode, insert filler, insert metal filler, add redundant via …);
- signoff flow ( StarRCXT, PT, DRC, LVS).
ASIC Design Flow In Brief
- chip specification;
- front end modeling, use C, C++ or System C/system verilog to do the modeling and simulation;
- design implementation in front end, verilgo or VHDL ;
- simulation;
- FPGA verification(optional);
- Synthesis, Design compiler , RTL to gate level netlist;
- Physical implementation.
Continue reading “ASIC Design Flow In Brief”
Mapping File: Database Layer <==> Process Layer
Maps File:
Map database layers to process layers conducting_layers, via_layers, marker_layers, remove_layers.
Layer Information:
Resistance information is optional: RPSQ (for conductors) or RPV (for vias) overrides process file, if specified
Continue reading “Mapping File: Database Layer < ==> Process Layer”
长音与旋律循环换气 zz
此种循环换气是所有循环换气的基础和前提，不掌握这种换气法，其它两种循环换气就无法学会。
Continue reading “长音与旋律循环换气 zz”
Interconnect Technology File (ITF)
What’s ITF:
ITF stands for Interconnect Technology File.
It contains a description of the process cross-section and connectivity section.
It describes the thicknesses and physical attributes of the conductor and dielectric layers.
It used to extract RC value for the chip.
It can be used to generate TLU TLUPlus files.
ITF file example http://gudonghua.googlepages.com/itf-file-example.itf.txt