Just joined a project lead by US team. The project leader and top designer have more than 15 years experience in backend design. It’s a good opportunity to learn from them. I will take notes on design methods for the whole project.
Just joined a project lead by US team. The project leader and top designer have more than 15 years experience in backend design. It’s a good opportunity to learn from them. I will take notes on design methods for the whole project.
The first thing to do is to check netlists, when you got a new netlist.
Following is some common items to check for a new netlist.
Raw Netlist
- TODO: cell count on netlist all cells, *222*, *32*, *22*, *DF*, MUX*
- TARGET: a very quick look for HHM’s with potential issues due to cell types.
Spotlight (pre-test)
- Gate count stats
- high fanout/fanon logic that causes congestion
- registered in/out ports potential HHM-to-toplevel-to-HHM timing issues
ICC (pre-test)
SWAP ‘X05’ Cells:
- TODO: hack the netlist to swap “X05” cells to “X1”
- TARGET: sed ‘s/X05/X1/’, prevent netlist timing issues caused by "X05" cells
Remove Buffer Tree:
- remove_buffer_tree -all
- helps when tracing the netlist, help initial placement
Convert AO22X/AOI22X that act as MUX’es to MUX cells
- Help congestion issue, need double check.
50% util square NxN layout
- PR starting point
- study hierarchy memory grouping/placement
"create_placement -congestion" (no timing)
- Global Route and Detail Route
- how does the number of DRC track with % GR. is 0.2% GRC okay or is 0.02% okay.
- Note: during bench mark work the location of GRC’s tracked with the location of DRC’s when detail routed
- look for scenic routes. scripts available to help with this.
- will there be routing issues
- track phase 3 GRC and total wire length
list of HHM pin names
- what are the names of the wide busses
- what busses are related, what should be placed together and in what order
- initially use pin guides for pin placement
High Fanin/Fanout Cones
- check high fanin/fanout cones reported by Spotlight
- potential congestion spots?
Special Structures
Unregistered Ports fanin/fanout
- potential HHM-to-toplevel-to-HHM timing issues
mem-to-port or port-to-mem ports
- potential HHM floor planning constraints
mem_inst_A-to-flop-to-mem_inst_A paths
- potential timing issue that can constrain floor planning?
large flop families example “blah/blah_blah/some_reg_2873”
these were related to congestion spots
look for “the pattern”
0,32,64,96,128…2016 => fanin to a flop or family of flops
1,33,65,97,129…2017 => fanin to a flop or family of flops
.
31,63,95,127,159…2047 => fanin to a flop or family of flops
list of large/major hierarchy
- what’s in the block
- ecc logic?